The present invention relates to Compact Peripheral Component Interconnect (cPCI) bus architecture and, more particularly, to systems for bridging cPCI bus segments on a backplane and coupling Single Board Computers (SBCs) to the backplane.
PCI (Peripheral Component Interconnect) is the dominant bus architecture for computers that are based upon Intel and comparable microprocessors. This architecture is used in several applications including PC motherboards, passive backplane systems, and CompactPCI (cPCI). The PCI architecture is limited in terms of the number of PCI load devices on expansion boards that any given bus segment can support. When an application requires more expansion devices than a given bus segment can support, the use of a PCI to PCI Bridge is required. The PCI to PCI Bridge acts as a repeater and amplifies the bus signals so that the bus signals can be provided to additional expansion devices. For passive backplane architecture, the addition of a bridge to the backplane is relatively simple. Usually, there is ample space on the backplane itself to place the bridge components and to route the traces necessary for proper connection of the bridge to the remainder of the backplane. For cPCI architecture, however, where the number of slots that are available on the backplane for coupling devices to the backplane is a valuable feature and active circuitry on the backplane is discouraged, insufficient room exists on the backplane to place bridge components on the backplane itself.
At least two strategies are currently known for adding a bridge to a backplane having cPCI architecture. Both of these strategies involve placing the bridge components on a daughter board that plugs into the backplane. Referring to FIG. 1, one prior art system employs a single circuit board 20 with bridging components that connects at two points to a backplane 10 having multiple slots 12 (pins in slots not shown) including slots 12a-12h. Specifically, the circuit board 20 connects to the rear of the backplane 10 at two of the slots 12d and 12h, and is mounted parallel to the backplane between those slots. Because the circuit board 20 connects to two separate slots 12d and 12h, which in the embodiment of FIG. 1 are positioned four slots apart from one another, this bridge implementation is commonly termed a xe2x80x9cmezzanine bridgexe2x80x9d. Turning to FIGS. 2 and 3, a second known system for bridging bus segments on a backplane having cPCI architecture employs one or more circuit boards 30 that extend from the backplane 10 at right angles to the backplane. The one or more circuit boards 30 can plug into the backplane 10 from either the front or rear of the backplane. This bridge implementation can be termed a xe2x80x9cplug-in card bridgexe2x80x9d.
Although both of these bridge systems provide functional bus expansion, both systems have significant undesirable effects. First, both systems reduce the total number of slots that are available on a backplane for connection to expansion devices. This is due to the nature of cPCI architecture. In accordance with cPCI architecture, the backplane 10 must have a system slot followed by 1 to 7 expansion slots. For example, with reference to FIG. 1, the backplane 10 includes a system slot 12a followed by 7 successive expansion slots 12b-12h. The system slot 12a is the location at which a system board, usually a Single Board Computer (SBC) which has the main system processor, is connected to the backplane 10. The system slot 12a is unique from the other slots in that all bus clocks, bus requests, bus grants, and other bus control signals originate at the system slot. Only the main system processor can be installed into the system slot 12a. 
As shown in FIG. 1, the circuit board 20 of the mezzanine bridge receives bus signals from the backplane 10 at slot 12d and outputs bus signals into the rear of the backplane slot 12h. Consequently, slot 12h effectively becomes a new system slot and cannot be connected to any expansion device. As a result, one expansion slot position is always lost when a mezzanine bridge is employed. A reduction in the number of available expansion slots can likewise occur when a plug-in card bridge is employed. Typically, at least one slot and sometimes two slots are required to accommodate the bridging board or boards in the plug-in card bridge implementation. For applications in which a maximum xe2x80x9cboard to slotxe2x80x9d count is required, these reductions in the number of available expansion slots on the backplane 10 due to bridging are not acceptable.
In addition to reducing the number of expansion devices that can be connected to a given backplane, both of the conventional strategies for bridging bus segments on a backplane compromise the input/output (I/O) possibilities of the cPCI architecture. Typically, the cPCI architecture allows xe2x80x9cpass throughxe2x80x9d I/O from boards that are connected to the slots 12 on the front of the backplane 10, to plug-in I/O transition boards connected to the rear of the backplane. However, when a mezzanine bridge is used, several slots typically become unavailable for use with the rear I/O transition boards. For example, in the embodiment shown in FIG. 1, four slots 12d-12g that could potentially be used for I/O transition boards are lost due to the positioning of the circuit board 20. In the case of the plug-in card bridge implementations of FIGS. 2 and 3, each of the slots 12 at which a circuit board 30 is connected to the backplane 10 is lost for use with 110 transitioning boards. That is, one slot is lost with the embodiment shown in FIG. 2, and two slots are lost with the embodiment shown in FIG. 3.
The bridging of backplanes is only one situation in which the availability of slots of backplanes using the cPCI architecture is undesirably reduced. A similarly undesirable result occurs when it is necessary to connect a Single Board Computer (SBC) to a backplane and interface the SBC to multiple cPCI bus segments. Although the embodiment of FIG. 4 shows the SBC 40 to be coupled to four connectors 14a, 14b, 14d and 14e that are positioned along the single slot 12h, in alternate embodiments the SBC is coupled to two pairs of the connectors 14 that are positioned on two adjacent slots, e.g., connectors 14a and 14b of each of slots 12g and 12h. 
Each of the conventional strategies for attaching an SBC to a backplane can undesirably limit the slots that are available for connecting expansion devices to the backplane. Typically the SBC 40 has a significant width due to the CPU 42, which results in the SBC blocking access to one or more adjacent slots. For example, with reference to the embodiment shown in FIG. 4, the SBC 40 blocks access to slot 12g due to the width of the CPU 42. Further, in certain embodiments a daughter board (not shown) must additionally be coupled to the SBC 40 in order to allow proper routing of signals. The existence of the daughter board also results in an increased overall width of the SBC assembly such that access to an additional adjacent slot, e.g., slot 12i, is blocked.
The conventional strategies for attaching an SBC have other undesirable characteristics as well. For example, the SBC 40 of FIG. 4 requires at least five inches of extra trace length in the backplane for the second bus segment. This violates the 7.3xe2x80x3 trace length limit stated in the PCI Industrial Computers Manufacturers Group (PICMG) 2.0 R2.1 and R3.0 specifications for trace length for cPCI bus segments. Further, the configuration of the SBC 40 of FIG. 4 precludes the use of the upper two connectors for rear I/O. Additionally, in the case of an SBC assembly that includes a daughter board, the SBC assembly suffers from additional increased exposure to interference due to the impedance of stubs (not shown) that typically exist on the daughter board.
Therefore, it would be advantageous if a new system and method were developed for adding bridges to, and connecting SBCs to, backplanes designed in accordance with the cPCI architecture. In particular, it would be advantageous if the new system and method enabled the bridging of bus segments on a backplane, as well as the attachment of a SBC to a backplane, with less of a reduction in the number of slots along the backplane that are available for connection to expansion devices. Additionally, it would be advantageous if such a system and method required less of a reduction in the number of slots available for connection to I/O transitioning boards than conventional systems and methods and if the components of such systems and methods were less susceptible to outside interference than the components of conventional systems and methods. Further, it would be advantageous if the new system and method still conformed with existing standards relating to cPCI architecture.
The present invention provides a backplane in accordance with the cPCI architecture that can be configured to include one or more expanded slots in which 10-row connectors, as opposed to standard 7-row connectors, are employed. The routing of the backplane is configured to be capable of receiving the pins of 9 rows of the 10-row connectors at the expanded slots, as opposed to merely the pins of 7 rows of 7-row connectors. When it is desired to add a bridge to the backplane, 10-row connectors are provided on a rear side of the backplane. The pins of 6 rows of the 10-row connectors extend through the backplane into 7-row shrouds that are provided on a front side of the back plane. The shrouds and the extended pins effectively form standard 7-row connectors on the front side of the backplane. Further, the pins of 3 remaining rows of the 10-row connectors extend only into the backplane (the 10-row connectors only employ pins in 9 of their rows).
Given such a backplane structure, a bridge can be connected to the backplane structure at the 10-row connectors. Bus signals are input into the bridge via the pins of the 6 rows of the 10-row connectors which extend from the 10-row connectors into the 7-row shrouds. At the same time, the bus signals can still be additionally provided to an expansion device connected to the 7-row connectors formed by the 7-row shrouds and the extended pins on the front side of the backplane. Therefore, the present invention allows bus signals to be provided to an input of a bridge without precluding connection of an expansion device at the same slot location along the backplane. Further, the bus signals that are provided to the bridge, upon being amplified and processed by the bridge, are returned to the backplane via the pins of the 3 remaining rows of the 10-row connectors. Consequently, the reduction in the number of slots available for I/O connection along the back side of the backplane is limited to a loss of at most one slot.
When it is desired to couple a SBC to the backplane, 10-row connectors are provided on the front side of the backplane, in place of 7-row connectors. Pins from 9 of the rows of the 10-row connectors extend from the 10-row connectors into the backplane. Pins from 6 of those rows receive signals from the SBC concerning a first bus signal to be provided by the backplane to a first set of slots, at which expansion devices can be connected to the backplane. The pins of the 3 remaining rows of pins of the 10-row connectors receive signals from the SBC concerning a second bus signal to be provided by the backplane to a second set of slots, at which expansion devices can also be connected to the backplane. Through the use of the 10-row connectors, the SBC requires coupling to fewer connectors, does not require coupling to multiple connectors positioned along the entire (or nearly the entire) length of a slot, and does not require a daughter board. Consequently, the SBC can be connected to the backplane with less of a reduction in the number of slots that are available for connection to expansion devices, in conformance with the PICMG specifications, and with less exposure to interference, than occurs with conventional systems.
In particular, the present invention relates to a backplane assembly in accordance with cPCI bus architecture, which includes a backplane having a front side and a back side, a plurality of 7-row connectors, at least one 7-row shroud coupled to the front side of the backplane, and at least one 10-row connector. The plurality of 7-row connectors are coupled to the front side of the backplane, and each of the 7-row connectors includes a plurality of pins that extend from within an interior of the backplane out through the front side of the backplane into the respective 7-row connector. The at least one 10-row connector is coupled to the back side of the backplane, and includes a plurality of extended pins that extend from within the interior of the backplane out through the front side of the backplane into the at least one 7-row shroud and out through the back side of the backplane into the at least one 10-row connector.
The present invention additionally relates to a backplane assembly in accordance with cPCI bus architecture, which includes a backplane and a plurality of slots on backplane at which the backplane is configured to be coupled to connectors placed along a first side of the backplane. The backplane assembly further includes a plurality of 7-row connectors coupled to the first side of the backplane at some of the slots, wherein each of the 7-row connectors includes a plurality of pins that extend from within an interior of the backplane out through the first side of the backplane into the respective 7-row connector. The backplane assembly additionally includes a 10-row connector coupled to the first side of the backplane at a respective one of the slots. The 10-row connector includes a plurality of pins that extend from within the interior of the backplane out through the first side of the backplane into the 10-row connector.
The present invention further relates to a backplane assembly in accordance with cPCI bus architecture, which includes a backplane having a first surface and a second surface, and a 10-row slot in the backplane. The 10-row slot includes at least 9 rows of pin locations at which the backplane is configured to receive pins extending transversely into the backplane from at least one of the first surface of the backplane and the second surface of the backplane. The backplane assembly additionally includes a plurality of 7-row slots in the backplane, each of the 7-row slots including 7 rows of pin locations at which the backplane is capable of receiving pins extending transversely into the backplane from at least the first surface of the backplane. At least a first 7-row slot exists on a first side of the 10-row slot and at least a second 7-row slot exists on a second side of the 10-row slot. The backplane assembly further includes a routing means for coupling at least some of the pin locations of the at least 9 rows of the 10-row slot with at least some of the pin locations of at least some of the 7 rows of at least some of the 7-row slots. The backplane assembly additionally comprises a plurality of connectors positioned adjacent to at least some of the 7-row slots and the 10-row slot.
The present invention also relates to a method of bridging a first bus signal on a backplane assembly. The method comprises providing a backplane with a 10-row slot having at least 9 rows of pin locations, and attaching a 7-row shroud to the 10-row slot along a front side of the backplane. The method additionally comprises attaching a 10-row connector to the 10-row slot along a back side of the backplane, wherein the 10-row connector includes at least 6 rows of pins that extend from the 10-row connector through the backplane into the 7-row shroud, and wherein the 10-row connector further includes at least 3 rows of pins that extend from the 10-row connector into the backplane, the backplane assembly including the backplane, the 7-row shroud and the 10-row connector. The backplane assembly is capable of being coupled to a bridge at the 10-row connector along the back side of the backplane, providing the first bus signal to the bridge by way of the at least 6 rows of pins by way of a plurality of routing connections supported by the backplane, and receiving a processed bus signal at the backplane from the bridge by way of the at least 3 rows of pins.
The present invention further relates to a method of providing a first bus signal and a second bus signal from a SBC to a backplane assembly. The method comprises providing a backplane with a first slot having at least 9 rows of pin locations including a first set of 6 rows of pin locations and a second set of 3 rows of pin locations, and providing on the backplane second and third slots respectively positioned on first and second sides of the first slot, the second and third slots each having at least 7 rows of pin locations. The method additionally comprises attaching a 10-row connector to the first slot along a front side of the backplane, wherein the 10-row connector includes a first set of 6 rows of pins and a second set of 3 rows of pins that are respectively coupled to the first and second sets of pin locations, and attaching at least one 7-row connector to each of the second and third slots. The method further comprises providing a set of routing connections within the backplane coupling the first set of 6 rows of pin locations and the second set of 3 rows of pin locations to the at least 7 rows of pin locations at the second and third slots, respectively. The backplane assembly is capable of being coupled to the SBC at the 10-row connector, receiving the first bus signal at the first set of 6 rows of pins and receiving the second bus signal at the second set of 3 rows of pins.